| Issue |
128078
|
| Summary |
"Unimplemented combination of reg class/subreg idx" while building eigen
|
| Labels |
backend:Hexagon
|
| Assignees |
iajbar
|
| Reporter |
androm3da
|
`UNREACHABLE` while building `eigen/test/product_trsolve.cpp` from https://gitlab.com/libeigen/eigen/
It'd be great if we could find a way to fix this for the 20.x release, @iajbar. Note that this reduced test case does not fail downstream.
```
$ ./bin/llc -O2 --mtriple=hexagon reduced.ll
Reg class id: 20 idx: 1
Unimplemented combination of reg class/subreg idx
UNREACHABLE executed at /local/mnt/workspace/upstream/llvm-project/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp:153!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: ./bin/llc -O2 --mtriple=hexagon reduced.ll
1. Running pass 'Function Pass Manager' on module 'reduced.ll'.
2. Running pass 'Hexagon Loop Rescheduling' on function '@_Z7trsolveIfLi4ELi1EEvii'
#0 0x000055c68d0fa348 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (./bin/llc+0x4625348)
#1 0x000055c68d0f7d90 llvm::sys::RunSignalHandlers() (./bin/llc+0x4622d90)
#2 0x000055c68d0faa61 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
#3 0x00007f83f503a520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
#4 0x00007f83f508e9fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
#5 0x00007f83f508e9fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10
#6 0x00007f83f508e9fc pthread_kill ./nptl/pthread_kill.c:89:10
#7 0x00007f83f503a476 gsignal ./signal/../sysdeps/posix/raise.c:27:6
#8 0x00007f83f50207f3 abort ./stdlib/abort.c:81:7
#9 0x000055c68d068681 (./bin/llc+0x4593681)
#10 0x000055c68b66605e (./bin/llc+0x2b9105e)
#11 0x000055c68b67530f llvm::BitTracker::MachineEvaluator::getRegBitWidth(llvm::BitTracker::RegisterRef const&) const BitTracker.cpp:0:0
#12 0x000055c68b665c21 llvm::HexagonEvaluator::mask(llvm::Register, unsigned int) const HexagonBitTracker.cpp:0:0
#13 0x000055c68b6781d8 llvm::BitTracker::MachineEvaluator::evaluate(llvm::MachineInstr const&, std::__1::map<unsigned int, llvm::BitTracker::RegisterCell, std::__1::less<unsigned int>, std::__1::allocator<std::__1::pair<unsigned int const, llvm::BitTracker::RegisterCell>>> const&, std::__1::map<unsigned int, llvm::BitTracker::RegisterCell, std::__1::less<unsigned int>, std::__1::allocator<std::__1::pair<unsigned int const, llvm::BitTracker::RegisterCell>>>&) const BitTracker.cpp:0:0
#14 0x000055c68b6714bf llvm::HexagonEvaluator::evaluate(llvm::MachineInstr const&, std::__1::map<unsigned int, llvm::BitTracker::RegisterCell, std::__1::less<unsigned int>, std::__1::allocator<std::__1::pair<unsigned int const, llvm::BitTracker::RegisterCell>>> const&, std::__1::map<unsigned int, llvm::BitTracker::RegisterCell, std::__1::less<unsigned int>, std::__1::allocator<std::__1::pair<unsigned int const, llvm::BitTracker::RegisterCell>>>&) const HexagonBitTracker.cpp:0:0
#15 0x000055c68b6794bf llvm::BitTracker::visitNonBranch(llvm::MachineInstr const&) BitTracker.cpp:0:0
#16 0x000055c68b67b56b llvm::BitTracker::runEdgeQueue(llvm::BitVector&) BitTracker.cpp:0:0
#17 0x000055c68b67bbfd llvm::BitTracker::run() BitTracker.cpp:0:0
#18 0x000055c68b652f8c (anonymous namespace)::HexagonLoopRescheduling::runOnMachineFunction(llvm::MachineFunction&) HexagonBitSimplify.cpp:0:0
#19 0x000055c68c106cb3 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (./bin/llc+0x3631cb3)
#20 0x000055c68c68a8dc llvm::FPPassManager::runOnFunction(llvm::Function&) (./bin/llc+0x3bb58dc)
#21 0x000055c68c692cf2 llvm::FPPassManager::runOnModule(llvm::Module&) (./bin/llc+0x3bbdcf2)
#22 0x000055c68c68b445 llvm::legacy::PassManagerImpl::run(llvm::Module&) (./bin/llc+0x3bb6445)
#23 0x000055c68b1b02f8 compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#24 0x000055c68b1adbad main (./bin/llc+0x26d8bad)
#25 0x00007f83f5021d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
#26 0x00007f83f5021e40 call_init ./csu/../csu/libc-start.c:128:20
#27 0x00007f83f5021e40 __libc_start_main ./csu/../csu/libc-start.c:379:5
#28 0x000055c68b1a9be5 _start (./bin/llc+0x26d4be5)
Aborted (core dumped)
```
reduced test case:
```
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown-linux-musl"
define void @_Z7trsolveIfLi4ELi1EEvii(ptr %cmRhs, i32 %0, i64 %retval.sroa.2.0.insert.ext.i) #0 personality ptr null {
entry:
%1 = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 %0)
call void @llvm.hexagon.V6.vS32b.nqpred.ai.128B(<128 x i1> zeroinitializer, ptr null, <32 x i32> %1)
%retval.sroa.2.0.insert.ext.i1 = zext i32 %0 to i64
%retval.sroa.2.0.insert.shift.i = shl i64 %retval.sroa.2.0.insert.ext.i, 32
%retval.sroa.0.0.insert.insert.i = or i64 %retval.sroa.2.0.insert.shift.i, %retval.sroa.2.0.insert.ext.i1
store i64 %retval.sroa.0.0.insert.insert.i, ptr %cmRhs, align 8
ret void
}
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
declare void @llvm.hexagon.V6.vS32b.nqpred.ai.128B(<128 x i1>, ptr, <32 x i32>) #1
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32>, <32 x i32>, i32) #2
; uselistorder directives
uselistorder ptr null, { 1, 2, 3, 0 }
attributes #0 = { "target-features"="+hvx-length128b,+hvxv68,+v60,-long-calls" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
```
cc @cantonios
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