| Issue |
125189
|
| Summary |
[X86] Failure to recognise hidden <2 x i64> ashr
|
| Labels |
backend:X86,
missed-optimization
|
| Assignees |
|
| Reporter |
RKSimon
|
Prior to AVX512, we were missing ASHR for i64 vectors, resulting in hacks like this:
```c
__m128i sra63(__m128i x) {
return _mm_srai_epi32(_mm_shuffle_epi32(x,_MM_SHUFFLE(3,3,1,1)),31);
}
```
```ll
define <2 x i64> @sra63(<2 x i64> %x) {
entry:
%0 = bitcast <2 x i64> %x to <4 x i32>
%1 = ashr <4 x i32> %0, <i32 0, i32 31, i32 0, i32 31>
%2 = shufflevector <4 x i32> %1, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
%3 = bitcast <4 x i32> %2 to <2 x i64>
ret <2 x i64> %3
}
```
which makes it incredibly difficult for other optimizaions to recognise whats going on - it'd be very useful if the middle end could convert these patterns back to a <2 x i64> ashr
```ll
define <2 x i64> @sra63(<2 x i64> %x) {
entry:
%0 = ashr <2 x i64> %x, <i64 63, i64 63>
ret <2 x i64> %0
}
```
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