| Issue |
122974
|
| Summary |
[llvm-exegesis][RISCV] computeAliasingInstructions in SerialSnipperGenerate generates instructions that can't be assembled
|
| Labels |
backend:RISC-V,
tools:llvm-exegesis
|
| Assignees |
|
| Reporter |
topperc
|
I tried to run through all RISC-V opcodes available on my SiFive P550 system using -opcode-index=-1. I got some crashes trying to assemble pseudo instructions.
Should llvm-exegesis be filtering pseudos and custom insertion instructions in this function?
CC: @boomanaiden154 @mshockwave
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