| Issue |
122767
|
| Summary |
[HLSL] RWBuffer resource variable has external linkage
|
| Labels |
new issue
|
| Assignees |
s-perron
|
| Reporter |
s-perron
|
When trying to compile an HLSL file with a resource, the compiler generates a variable to hold the handle to the resource. That variable is not actually the resource, and I believe it should have internal linkage, so that the optimizer could remove all references to it. See https://godbolt.org/z/v559r6axr
```
RWBuffer<int4> buffer : register(u2);
[numthreads(1,1,1)]
void main()
{
buffer[0] = 0;
}
```
This turns into:
```
@buffer = local_unnamed_addr global %"class.hlsl::RWBuffer" zeroinitializer, align 4, !dbg !0
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(write, inaccessiblemem: none)
define void @main() local_unnamed_addr #0 {
%1 = tail call target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i32_1_0_0t(i32 0, i32 2, i32 1, i32 0, i1 false), !dbg !45
store target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) %1, ptr @buffer, align 4, !dbg !45
#dbg_value(ptr @buffer, !49, !DIExpression(), !54)
#dbg_value(i32 0, !52, !DIExpression(), !54)
%2 = tail call noundef nonnull align 16 dereferenceable(16) ptr @llvm.dx.resource.getpointer.p0.tdx.TypedBuffer_v4i32_1_0_0t(target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) %1, i32 0), !dbg !54
store <4 x i32> zeroinitializer, ptr %2, align 16, !dbg !59, !tbaa !60
ret void
}
```
Note the store to `@buffer` was not removed. This causes problems for the SPIR-V backend:
1. We cannot remove the store to `@buffer` in the backend because it could be externally visible.
2. SPIR-V has a concept of externally visible variable, but it is not allowed in Vulkan.
Is there anything we can do to allow the optimizer to remove the store?
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