| Issue |
119921
|
| Summary |
[AArch64] Failure to combine bitwise not of shift into `mvn`
|
| Labels |
backend:AArch64,
missed-optimization
|
| Assignees |
|
| Reporter |
Kmeakin
|
https://godbolt.org/z/7sKhdbr4E
The `mvn` (move-not) instruction produces the bitwise not of a shifted/rotated register. GCC recognizes this pattern and produces `mvn`, but clang does not
clang:
```asm
mvn_lsl_1_u8(unsigned char):
mov w8, #-1
eor w0, w8, w0, lsl #1
ret
mvn_lsl_1_u16(unsigned short):
mov w8, #-1
eor w0, w8, w0, lsl #1
ret
mvn_lsl_1_u32(unsigned int):
mov w8, #-1
eor w0, w8, w0, lsl #1
ret
mvn_lsl_1_u64(unsigned long):
mov x8, #-1
eor x0, x8, x0, lsl #1
ret
```
GCC:
```asm
mvn_lsl_1_u8(unsigned char):
mvn w0, w0, lsl 1
ret
mvn_lsl_1_u16(unsigned short):
mvn w0, w0, lsl 1
ret
mvn_lsl_1_u32(unsigned int):
mvn w0, w0, lsl 1
ret
mvn_lsl_1_u64(unsigned long):
mvn x0, x0, lsl 1
ret
```
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