| Issue |
100848
|
| Summary |
[RISCV] Suboptimal build_vector lowering for bf16
|
| Labels |
backend:RISC-V
|
| Assignees |
|
| Reporter |
topperc
|
This test case lowers build_vector through memory with -mattr=+zvfbfmin,+zfbfmin
```
define <4 x bfloat> @foo(bfloat %a, bfloat %b, bfloat %c, bfloat %d) {
%1 = insertelement <4 x bfloat> poison, bfloat %a, i32 0
%2 = insertelement <4 x bfloat> %1, bfloat %b, i32 1
%3 = insertelement <4 x bfloat> %2, bfloat %c, i32 2
%4 = insertelement <4 x bfloat> %3, bfloat %d, i32 3
ret <4 x bfloat> %4
}
```
```
foo: # @foo
.cfi_startproc
# %bb.0:
addi sp, sp, -16
.cfi_def_cfa_offset 16
fsh fa3, 14(sp)
fsh fa2, 12(sp)
fsh fa1, 10(sp)
fsh fa0, 8(sp)
addi a0, sp, 8
vsetivli zero, 4, e16, m2, ta, ma
vle16.v v8, (a0)
addi sp, sp, 16
ret
```
We need to enable custom lowering for BUILD_VECTOR and probably cast the build_vector to the equivalent i16 build_vector.
If we have Zvfh, we can use vfslide1down.vf instructions. Not sure if we should bitcast it to an f16 vector or add isel patterns for bf16 slide with Zvfh+Zvfbfmin.
CC: @jacquesguan @wangpc-pp @preames
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