| Issue |
97943
|
| Summary |
[Hexagon]Enhance the handling of addrspacecast conversions.
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
DigOrDog
|
# Description
The below IR code compiles successfully on various architectures including AArch64, x86_64, ARM, Berkeley Packet Filter (BPF), NVIDIA Parallel Thread Execution (NVPTX64), PowerPC, and RISC-V64. However, it encounters compilation issues specifically on the Hexagon architecture. There is a consideration of whether it is essential to strengthen the handling of such cases to ensure compatibility and robustness across all targeted architectures.
https://godbolt.org/z/ja8W85Pjv
# IR
llc in.ll -mtriple=hexagon -mcpu=generic -mattr=+nvs
```
define double @f(ptr %G, ptr %x) {
BB:
%Castaddrspacecast = addrspacecast ptr %x to ptr addrspace(1)
store ptr addrspace(1) %Castaddrspacecast, ptr %G, align 8
ret double 0.000000e+00
}
```
![]()
_______________________________________________
llvm-bugs mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
