| Issue |
97821
|
| Summary |
[AArch64] Get different assemble for code which doesn't use sve register
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
vfdff
|
* test: https://gcc.godbolt.org/z/Mn6ob7efq
```
#define difference_type long long
void foo1();
extern long long __begin_, __first_;
int foo (long long a[]) {
if (__begin_ > __first_) {
difference_type __d = __begin_ - __first_;
__d = (__d + 1) / 2;
__begin_ -= __d;
}
return 0;
}
```
* the above code split from **llvm-project/libcxx/include/__split_buffer**, we can see the final assemble doesn't include sve register, but it generate different assemble for code with/without **+sve**. For the sve version, it even use a **sdiv** instruction for **__d = (__d + 1) / 2;**
> with sve
```
foo: // @foo
adrp x8, :got:__begin_
adrp x10, :got:__first_
ldr x8, [x8, :got_lo12:__begin_]
ldr x10, [x10, :got_lo12:__first_]
ldr x9, [x8]
ldr x10, [x10]
subs x10, x9, x10
b.le .LBB0_2
add x10, x10, #1
mov x11, #-2 // =0xfffffffffffffffe
sdiv x10, x10, x11
add x9, x10, x9
str x9, [x8]
.LBB0_2:
mov w0, wzr
ret
```
> without sve
```
foo: // @foo
adrp x8, :got:__begin_
adrp x10, :got:__first_
ldr x8, [x8, :got_lo12:__begin_]
ldr x10, [x10, :got_lo12:__first_]
ldr x9, [x8]
ldr x10, [x10]
subs x10, x9, x10
b.le .LBB0_2
add x11, x10, #1
add x12, x10, #2
cmp x11, #0
csinc x10, x12, x10, lt
sub x9, x9, x10, asr #1
str x9, [x8]
.LBB0_2:
mov w0, wzr
ret
```
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