[llvm-bugs] [Bug 96490] What is `${p}` clober in some instructions definition of ARMv8.1-M instruction tabelgen?

[LLVM Bugs via llvm-bugs]

Issue	96490
Summary	What is `${p}` clober in some instructions definition of ARMv8.1-M instruction tabelgen?
Labels	new issue
Assignees
Reporter	ChoKyuWon

    I found that the new ARMv8.1-M ISA instructions table gen generates weird code.
For example, the PACG definitions is like this:
```
let hasSideEffects = 1 in {
class PACBTIAut<dag iops, string asm, bit b>
  : V8_1MI<(outs), iops,
           AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {
  bits<4> Ra;
 bits<4> Rn;
  bits<4> Rm;
  let Inst{31-20} = 0b111110110101;
  let Inst{19-16} = Rn;
  let Inst{15-12} = Ra;
  let Inst{11-5}  = 0b1111000;
  let Inst{4}     = b;
  let Inst{3-0}   = Rm;
}
}

def t2AUTG  : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, GPRnopc:$Rn, GPRnopc:$Rm),
                        "autg${p}", 0>;
```
And it omits the following emitter:
```C++
uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
 SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
...
    case ARM::t2AUTG:
    case ARM::t2BXAUT: {
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
 op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
 break;
    }
```

So my question is: why do we need `${p}` for the first ins argument, and what are the first and second operands of MI?
Can we just remove all of {p} there and sort the operand order as normal instructions?

Here is the reference: https://developer.arm.com/documentation/ddi0553/latest/ and I cannot find any difference between `AUTG` and `MUL` in term of Instruction encoding, and want sure that is intended feature.

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