Issue |
95284
|
Summary |
[RISCV] Regression due to creation of avgfloors nodes
|
Labels |
backend:RISC-V,
llvm:codegen
|
Assignees |
RKSimon
|
Reporter |
RKSimon
|
```ll
; llc -mtriple=riscv64 test.ll -o -
define signext i64 @func000000000000002b(i32 signext %0) #0 {
entry:
%1 = zext nneg i32 %0 to i64
%2 = add nsw i64 %1, -1
%3 = lshr i64 %2, 1
%4 = add nuw nsw i64 %3, 1
%5 = and i64 %4, 9223372036854775806
ret i64 %5
}
```
Before:
```asm
func000000000000002b:
addi a0, a0, -1
srli a0, a0, 1
addi a0, a0, 1
andi a0, a0, -2
ret
```
After:
```asm
func000000000000002b:
addi a0, a0, -1
srli a0, a0, 1
addi a0, a0, 1
li a1, -3
srli a1, a1, 1
and a0, a0, a1
ret
```
Reported by @dtcxzyw on #92096
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs