| Issue |
90513
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| Summary |
[RISCV] Backend not generating temp registers, uses argument registers instead
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| Labels |
new issue
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| Assignees |
|
| Reporter |
Peppy3
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# Temp registers not used in code generation
I've played around a bit in Godbolts Compiler Explorer and seen that the code generator does not generate any temp registers (t0 - t6) specified in the RiscV ABI and uses the argument registers instead. It makes an improvement in readability of the generated assembly and a possible speed-up as less cache access is needed in some circumstances.
I have tried to compile to target riscv64-linux-gnu with Clang version 14.0.0-1ubuntu1.1 on my x86_64 pc running Linux Mint 21.2 to no avail (it trips on some library that doesn't exist on my system (I think it's because I don't have target libc)) but I don't think I need to show code to convince anyone.
Is this argument registers as temporaries thing intentional? And if so, why?
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