| Issue |
89971
|
| Summary |
AMDGPU inline assembly with s constraint incorrectly emits VGPR use
|
| Labels |
backend:AMDGPU
|
| Assignees |
|
| Reporter |
arsenm
|
https://godbolt.org/z/Yonee4P1G
```
define hidden i32 @test(i32 noundef %mask) local_unnamed_addr #0 {
entry:
%tobool = icmp ne i32 %mask, 0
%0 = tail call i64 @llvm.amdgcn.ballot.i64(i1 %tobool)
%cmp = icmp eq i64 %0, 0
%conv = zext i1 %cmp to i32
%1 = tail call i32 asm sideeffect "s_mov_b32 $0, $1", "=s,s"(i32 %conv) #2
ret i32 %1
}
```
This is incorrectly emitting a VGPR for the use operand `s_mov_b32 s0, v0`
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