| Issue |
89830
|
| Summary |
Implicit Exec Mask Operand Missing From MCInstrDesc of Some Opcodes in AMDGPU backend
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
matinraayai
|
The following Opcodes do not have `AMDGPU::EXEC` mask as an implicit operand in their MC Instr Desc:
`GLOBAL_STORE_DWORD_vi`
`BUFFER_LOAD_DWORD_OFFEN_vi`
`GLOBAL_STORE_DWORD_SADDR_vi`
The issue appears when constructing a `llvm::MachineInstr` from a valid `llvm::MCInst`, in the same manner as llvm-exegesis here:
https://github.com/llvm/llvm-project/blob/859de94536425376244940e190e069a09d797737/llvm/tools/llvm-exegesis/lib/Assembler.cpp#L157-L176
For the MIR to be correct, simply adding the explicit operands should be enough, as the implicit operands are automatically added according to the MCInstrDesc when calling the `llvm::BuildMI` here:
https://github.com/llvm/llvm-project/blob/859de94536425376244940e190e069a09d797737/llvm/tools/llvm-exegesis/lib/Assembler.cpp#L157
This method will call the `llvm::MachineInstr` constructor with `NoImplicit` flag set to `false`:
https://github.com/llvm/llvm-project/blob/859de94536425376244940e190e069a09d797737/llvm/lib/CodeGen/MachineInstr.cpp#L98-L114
However, when printing the constructed MIR, the implicit exec is nowhere to be seen:
```
GLOBAL_STORE_DWORD_vi $vgpr0_vgpr1, $vgpr2, 0, 0
BUFFER_LOAD_DWORD_OFFEN_vi $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0
BUFFER_STORE_DWORD_OFFEN_vi $vgpr1, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0
```
This causes issues when these instructions get verified before running CodeGen passes.
CC: @arsenm @kzhuravl
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