| Issue |
89822
|
| Summary |
RISC-V Machine Outliner should reach parity with other platforms
|
| Labels |
enhancement,
backend:RISC-V,
llvm:codegen,
llvm:codesize
|
| Assignees |
|
| Reporter |
ilovepi
|
Machine Outliner can lead to significant size savings, even for 32-bit embedded targets, see https://www.linaro.org/blog/reducing-code-size-with-llvm-machine-outliner-on-32-bit-arm-targets/
Both Arm and AArch64 backends support variety of outlining strategies:
https://github.com/llvm/llvm-project/blob/89c95effe82c09b9a42408f4823409331f8fa266/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp#L5678-5778
https://github.com/llvm/llvm-project/blob/89c95effe82c09b9a42408f4823409331f8fa266/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp#L8099-L8178
While the RISC-V backend has some outlining support, it's fairly limited compared to Arm and AArch64 backends, see https://github.com/llvm/llvm-project/blob/89c95effe82c09b9a42408f4823409331f8fa266/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp#L2533-L2570
We should improve the RISC-V Machine Outliner to be on par with Arm and AArch64.
Off the top of my head we should take the following steps:
1. Perform Gap analysis between the ARM and RISC-V machine outliners
1. Discuss the findings with RISC-V backend maintainers: @topperc @preames @MaskRay @asb @jrtc27
1. Create a design implementation plan to improve support
1. Implement improved support upstream
CC: @petrhosek
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