https://bugs.llvm.org/show_bug.cgi?id=51627
Bug ID: 51627
Summary: [AArch64][MIScheduler] UseAA incorrectly reordering
struct load and store that alias
Product: new-bugs
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: cameron.mcina...@nyu.edu
CC: david.gr...@arm.com, htmldevelo...@gmail.com,
llvm-bugs@lists.llvm.org, paul.wal...@arm.com
Created attachment 25194
--> https://bugs.llvm.org/attachment.cgi?id=25194&action=edit
Reduced test case
The attached test case miscompiles at -O1:
> llc test.ll -O1 -mcpu=carmel
This is a regression, found in release/13.x, from this commit:
>commit af342f72400445b85c38ba768439c495d7cf346f
>Author: David Green <david.gr...@arm.com>
>Date: Sat Apr 24 17:51:50 2021 +0100
>
>[AArch64] Enable UseAA globally in the AArch64 backend
>
>This is similar to D69796 from the ARM backend. We remove the UseAA
>feature, enabling it globally in the AArch64 backend. This should in
>general be an improvement allowing the backend to reorder more
>instructions in scheduling and codegen, and enabling it by default helps
>to improve the testing of the feature, not making it cpu-specific. A
>debugging option is added instead for testing.
The Machine Instruction Scheduler is reordering a load and store that alias:
.Ltmp2:
adrp x8, .S01101
add x8, x8, :lo12:.S01101
ldr w9, [x8]
str w9, [sp, #8]
ldrb w8, [x8, #4]
ldr x0, [sp, #8] <== HERE
strb w8, [sp, #12] <== AND HERE
bl foo
mov w0, wzr
ldr x30, [sp], #16 // 8-byte Folded Reload
ret
The 8b store to sp+12 should happen before the 64b load from sp+8.
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