https://bugs.llvm.org/show_bug.cgi?id=51365
Bug ID: 51365
Summary: [ARM][Thumb2] LowerCONCAT_VECTORS_i1 assumes
concatenation of only 2 vectors
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
Assignee: unassignedb...@nondot.org
Reporter: llvm-...@redking.me.uk
CC: david.gr...@arm.com, llvm-bugs@lists.llvm.org,
smithp...@googlemail.com, ties.st...@arm.com
I'm currently investigating adding this style of fold as an extension to
D107068:
concat(concat(x,y,z,w),concat(a,b,c,d)) -> concat(x,y,z,w,a,b,c,d)
This has exposed an issue with LowerCONCAT_VECTORS_i1 - it assumes that it only
ever has 2 operands:
static SDValue LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDLoc dl(Op);
EVT VT = Op.getValueType();
EVT Op1VT = V1.getValueType();
EVT Op2VT = V2.getValueType();
unsigned NumElts = VT.getVectorNumElements();
and with my fold the active_lane_mask.ll v16i8 test can now generate:
(v16i1 concat(v4i1,v4i1,v4i1,v4i1))
This needs generalizing to repeatedly concatenate pairs of subvectors together
using the existing lowering approach.
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