[llvm-bugs] [Bug 50512] New: AArch64 backend ignores failure ordering for cmpxchg

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=50512

            Bug ID: 50512
           Summary: AArch64 backend ignores failure ordering for cmpxchg
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedb...@nondot.org
          Reporter: efrie...@quicinc.com
                CC: arnaud.degrandmai...@arm.com,
                    llvm-bugs@lists.llvm.org, smithp...@googlemail.com,
                    ties.st...@arm.com

https://godbolt.org/z/jvnYzrPce

For the following testcase:

#include <stdatomic.h>
void test(_Atomic(int) *a, int b) {
        atomic_compare_exchange_weak_explicit(a, &b, 1, memory_order_relaxed,
memory_order_seq_cst); // undefined!
}

We generate (with --target=aarch64 -O2 -march=armv8.2-a):

test:
        mov     w8, #1
        cas     w1, w8, [x0]
        ret

This is pretty clearly wrong, especially with the most recent updates to the
C++ standard.

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