https://bugs.llvm.org/show_bug.cgi?id=50350
Bug ID: 50350
Summary: [MCA] Multiple Int schedulers
Product: tools
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: llvm-mca
Assignee: unassignedb...@nondot.org
Reporter: lebedev...@gmail.com
CC: andrea.dibia...@gmail.com, llvm-bugs@lists.llvm.org,
matthew.da...@sony.com
Currently, Znver3 models as-if the Int unit has a single scheduler
encompassing all the 9 pipes. This isn't quite right.
I would like to model it as:
```
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td
b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index 84aee73bad63..a7d369f55b74 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -163,15 +163,23 @@ def Zn3IntegerPRF : RegisterFile<192, [GR64, CCR], [1,
1], [1, 0],
// The schedulers can receive up to six macro ops per cycle, with a limit of
// two per scheduler. Each scheduler can issue one micro op per cycle into
// each of its associated pipelines
-// FIXME: these are 4 separate schedulers, not a single big one.
-def Zn3Int : ProcResGroup<[Zn3ALU0, Zn3AGU0, Zn3BRU0, // scheduler 0
- Zn3ALU1, Zn3AGU1, // scheduler 1
- Zn3ALU2, Zn3AGU2, // scheduler 2
- Zn3ALU3, Zn3BRU1 // scheduler 3
- ]> {
- let BufferSize = !mul(4, 24);
+def Zn3IntSch0 : ProcResGroup<[Zn3ALU0, Zn3AGU0, Zn3BRU0]> { // scheduler 0
+ let BufferSize = 24;
+}
+def Zn3IntSch1 : ProcResGroup<[Zn3ALU1, Zn3AGU1 ]> { // scheduler 1
+ let BufferSize = 24;
+}
+def Zn3IntSch2 : ProcResGroup<[Zn3ALU2, Zn3AGU2 ]> { // scheduler 2
+ let BufferSize = 24;
+}
+def Zn3IntSch3 : ProcResGroup<[Zn3ALU3, Zn3BRU1]> { // scheduler 3
+ let BufferSize = 24;
}
+def Zn3Int : ProcResGroup<[Zn3ALU0, Zn3AGU0, Zn3BRU0, // scheduler 0
+ Zn3ALU1, Zn3AGU1, // scheduler 1
+ Zn3ALU2, Zn3AGU2, // scheduler 2
+ Zn3ALU3, Zn3BRU1]>; // scheduler 3
//===----------------------------------------------------------------------===//
// Floating-Point Unit
```
The last `Zn3Int` is needed to silence the
```
FAILED: lib/Target/X86/X86GenSubtargetInfo.inc
cd /builddirs/llvm-project/build-Clang12 &&
/builddirs/llvm-project/build-Clang12/bin/llvm-tblgen -gen-subtarget -I
/repositories/llvm-project/llvm/lib/Target/X86
-I/builddirs/llvm-project/build-Clang12/include
-I/repositories/llvm-project/llvm/include -I
/repositories/llvm-project/llvm/lib/Target
/repositories/llvm-project/llvm/lib/Target/X86/X86.td --write-if-changed -o
lib/Target/X86/X86GenSubtargetInfo.inc -d
lib/Target/X86/X86GenSubtargetInfo.inc.d
Included from /repositories/llvm-project/llvm/lib/Target/X86/X86.td:562:
/repositories/llvm-project/llvm/lib/Target/X86/X86ScheduleZnver3.td:136:1:
error: proc resource group overlaps with Zn3IntSch0 but no supergroup contains
both.
def Zn3AGU012 : ProcResGroup<[Zn3AGU0, Zn3AGU1, Zn3AGU2]>;
^
```
But as a result, the Zn3IntSch0/Zn3IntSch1/Zn3IntSch2/Zn3IntSch3 appear to not
be used at all.
How would i approach this? The same problem exists for FP unit.
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