https://bugs.llvm.org/show_bug.cgi?id=49655
Bug ID: 49655
Summary: Masks on SIMD shift values should be elided
Product: libraries
Version: trunk
Hardware: PC
URL: https://github.com/WebAssembly/simd/issues/342#issueco
mment-802992866
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: WebAssembly
Assignee: tliv...@google.com
Reporter: tliv...@google.com
CC: llvm-bugs@lists.llvm.org
E.g. `vec << (count & 15)` will emit the AND, even though the shift already
takes care of it.
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