https://bugs.llvm.org/show_bug.cgi?id=49213
Bug ID: 49213
Summary: [MIScheduler] Bad machine code: Live segment doesn't
end at a valid instruction
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Common Code Generator Code
Assignee: unassignedb...@nondot.org
Reporter: pauls...@linux.vnet.ibm.com
CC: llvm-bugs@lists.llvm.org
Created attachment 24543
--> https://bugs.llvm.org/attachment.cgi?id=24543&action=edit
reduced testcase
llc -mcpu=arch13 -O3 -disable-machine-dce -verify-misched
tc_crash3_aftercreduce.ll
# Before machine scheduling.
********** INTERVALS **********
%0 [320r,320d:0) 0@320r weight:0.000000e+00
%1 [176r,224d:0) 0@176r weight:0.000000e+00
%3 [96r,176r:0) 0@96r weight:0.000000e+00
%12 [16r,32r:0) 0@16r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function f: NoPHIs, TracksLiveness, TiedOpsRewritten
0B bb.0.bb:
successors: %bb.2(0x80000000), %bb.1(0x00000000); %bb.2(100.00%),
%bb.1(0.00%)
16B %12:grx32bit = LHIMux 0
32B CHIMux %12:grx32bit, 0, implicit-def $cc
48B BRC 14, 6, %bb.2, implicit killed $cc
64B J %bb.1
80B bb.1.bb2:
; predecessors: %bb.0
96B %3:gr64bit = LGRL @b :: (dereferenceable load 8 from `i144* bitcast
(%0* @b to i144*)`)
176B %1:gr64bit = SRLG %3:gr64bit, $noreg, 16
320B dead %0:gr64bit = LGHI 0
336B bb.2.bb4:
; predecessors: %bb.0
352B Return
# End machine code for function f.
*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function: f
- basic block: %bb.1 bb2 (0x712edf0) [80B;336B)
- liverange: [176r,224d:0) 0@176r
- v. register: %1
- segment: [176r,224d:0)
LLVM ERROR: Found 1 machine code errors.
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