https://bugs.llvm.org/show_bug.cgi?id=45025
Bug ID: 45025
Summary: [entry values] ARM isCopyInstrImpl incorrect for VMOVS
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
Assignee: unassignedb...@nondot.org
Reporter: v...@apple.com
CC: llvm-bugs@lists.llvm.org, smithp...@googlemail.com,
ties.st...@arm.com
We get the following assertion failure when building ARM code:
Assertion failed: (!TRI->isSuperOrSubRegisterEq(Reg, DestReg) &&
"TargetInstrInfo::describeLoadedValue can't describe super- or " "sub-regs for
copy instructions"
The following instruction is passed to TargetInstrInfo::describeLoadedValue:
$s1 = VMOVS killed $s21, 14, $noreg, implicit-def $d0
ARMBaseInstrInfo::isCopyInstrImpl reports that this is a copy:
```
Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
if (MI.isCopy()) {
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
}
return isCopyInstrImpl(MI); // <- Reached.
}
=>
if (!MI.isMoveReg() ||
(MI.getOpcode() == ARM::VORRq &&
MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
return None;
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; // <- Reached.
```
According to TRI, llvm think that s1 is a sub-register of s21. I'm not sure
that's what the docs say:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/ch13s03s02.html
(this makes it look like s{0..31} are independent single-word registers).
Regardless, istm that ARMBaseInstrInfo::isCopyInstrImpl should be taking a
whitelisting approach, not a blacklist. I.e. we should not allow non-copy
instructions we haven't explicitly handled be treated as copies.
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