https://bugs.llvm.org/show_bug.cgi?id=38280
Bug 38280 depends on bug 40878, which changed state.
Bug 40878 Summary: Failure to reduce indvarsimplify modulo loop output to a
simple AND mask
https://bugs.llvm.org/show_bug.cgi?id=40878
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |FIXED
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