https://bugs.llvm.org/show_bug.cgi?id=44638
Bug ID: 44638
Summary: interleaved memory access blocking loop vectorization
Product: libraries
Version: 7.0
Hardware: Other
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AArch64
Assignee: unassignedb...@nondot.org
Reporter: w...@marvell.com
CC: arnaud.degrandmai...@arm.com,
llvm-bugs@lists.llvm.org, peter.sm...@linaro.org,
ties.st...@arm.com
Created attachment 23047
--> https://bugs.llvm.org/attachment.cgi?id=23047&action=edit
The attached file shows the loop cannot be vectorized because of the high cost
in interleaved memory access
In loop vectorizer, LV, the decision to vectorize a loop is based on the cost
of the vectorized loop. The cost is calculated on the each instruction in the
loop. For interleaved access instruction group, there is one cost for the whole
group. The cost is based on extract/insert model to implement the interleaved
memory access. Usually, this group cost will be very high, especially on
AArch64 which has has a VectorInsertExtractBaseCost set to 3 in
AArch64Subtarget.h. This high cost usually will fail the loop to be vectorized.
On AArch64, there are multiple ways to implement interleaved memory access
without using the vector extract/insert model. For example, TBL instruction can
be used to rearrange and dispatch data from a vector to form a new vector and
it is a single one instruction cost. Also one use zip1/2, umull1/2, smull1/2 to
do this same work instead of extract/insert model.
ti reproduce this problem, compile the attched file with this command
clang -mcpu=thunderx2t99 -march=armv8.1-a+lse -mllvm tbl3.c -ffast-math
-ffp-contract=fast -funroll-loops -finline-functions -fslp-vectorize
-fvectorize -O3 -o tbl3.out
The problem exists in all llvm versions.
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