https://bugs.llvm.org/show_bug.cgi?id=44467
Bug ID: 44467
Summary: [ARM][load / store optimization pass] Missed
optimization: coalesce pre-increment
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Keywords: missing-feature
Severity: enhancement
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: diogo.samp...@arm.com
CC: htmldevelo...@gmail.com, llvm-bugs@lists.llvm.org
Created attachment 22991
--> https://bugs.llvm.org/attachment.cgi?id=22991&action=edit
Minimal MIR case
Missed optimization:
When running
llc --print-before-all --start-before=arm-ldst-opt missed.mir -o -
we obtain:
push.w {r4, r5, r6, r7, r8, r10, r11, lr}
sub sp, #8
strd r0, r1, [sp] @ 8-byte Folded Spill
@ InlineAsm Start
@ InlineAsm End
ldrd r0, r1, [sp], #8 @ 8-byte Folded Reload
pop.w {r4, r5, r6, r7, r8, r10, r11, pc}
I would expect the strd to be pre-incremented, as:
push.w {r4, r5, r6, r7, r8, r10, r11, lr}
strd r0, r1, [sp, #-8]!
@ InlineAsm Start
@ InlineAsm End
ldrd r0, r1, [sp], #8
pop.w {r4, r5, r6, r7, r8, r10, r11, pc}
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