https://bugs.llvm.org/show_bug.cgi?id=44041
Bug ID: 44041
Summary: [MSP430][AVR][InstCombine][DAGCombine]Poor codegen for
targets with no native shifts (4/8)
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: unassignedb...@nondot.org
Reporter: joan.ll...@icloud.com
CC: llvm-bugs@lists.llvm.org
A number of comparisons involving bit tests are converted into shifts by
InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit
targets with comparatively cheaper selects.
It is desirable that selects are emitted instead of shifts for these targets.
The following cases were identified in TargetLowering and DAGCombine and were
fixed by:
https://reviews.llvm.org/D69116
https://reviews.llvm.org/D69120
https://reviews.llvm.org/D69326
https://reviews.llvm.org/D70042
Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that
these cases should be fixed by reversing the current canonicalisation. I am
showing them in this and following reports:
REPORTED CASE:
Source code:
int testExtendSignBit_1( int x ) // (InstCombineCasts::transformZExtICmp)
{
return x>-1 ? 1 : 0;
}
IR code:
define i16 @testExtendSignBit_1(i16 %x) {
entry:
%x.lobit = lshr i16 %x, 15
%x.lobit.not = xor i16 %x.lobit, 1
ret i16 %x.lobit.not
}
MSP430 Target code:
testExtendSignBit_1:
inv r12
swpb r12
mov.b r12, r12
clrc
rrc r12
rra r12
rra r12
rra r12
rra r12
rra r12
rra r12
ret
AVR Target code:
testExtendSignBit_1:
com r24
com r25
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
ret
EXPECTED RESULT:
Source code:
int testExtendSignBit_1( int x ) // (InstCombineCasts::transformZExtICmp)
{
return x>-1 ? 1 : 0;
}
Expected IR code:
define i16 @testExtendSignBit_1(i16 %x) {
entry:
%cmp = icmp sgt i16 %x, -1
%cond = zext i1 %cmp to i16
ret i16 %cond
}
Expected MSP430 Target code:
testExtendSignBit_1:
mov r12, r13
mov #1, r12
tst r13
jge .LBB3_2
clr r12
.LBB3_2:
ret
Expected AVR Target code:
testExtendSignBit_1:
ldi r18, 1
tst r25
brpl LBB3_2
ldi r18, 0
LBB3_2:
mov r24, r18
clr r25
ret
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