https://bugs.llvm.org/show_bug.cgi?id=43867
Bug ID: 43867
Summary: Invalid Hexagon disassembly with new-value operands
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: w.parker.thomp...@gmail.com
CC: htmldevelo...@gmail.com, llvm-bugs@lists.llvm.org
Reproduction:
echo "0x01, 0x43, 0x1d, 0xb0, 0x92, 0x43, 0x00, 0x00, 0x00, 0x43, 0x00, 0x78,
0x01, 0xd5, 0xbd, 0xa1" | llvm-mc -disassemble -triple=hexagon
Result:
<stdin>:1:1: warning: invalid instruction encoding
0x01, 0x43, 0x1d, 0xb0, 0x92, 0x43, 0x00, 0x00, 0x00, 0x43, 0x00, 0x78, 0x01,
0xd5, 0xbd, 0xa1
Expected disassembly:
{
r1 = add(r29,#24)
r0 = ##58520
memw(r29+#4) = r1.new
}
Possible cause (speculation):
The bug appears to be at:
https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L488
The disassembler fetches the register enum value and not the Nt bits from the
instruction itself (location varies by instruction). This means when the
SubregBit is checked, it will fail the check at line:
https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L501
for every odd register (like the example above).
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