https://bugs.llvm.org/show_bug.cgi?id=41983
Bug ID: 41983
Summary: Scheduling info for DIV narrower than 64-bits is wrong
on Skylake Server (and I assume Skylake Client too)
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected]
LLVM believes that 16, 32, and 64-bit divs on Skylake Server have a latency of
76 cycles and a throughput of one per 11 cycles:
https://github.com/llvm-mirror/llvm/blob/d8286e45afd6b6a8d34f3002f884b00e64406857/lib/Target/X86/X86SchedSkylakeServer.td#L141
However, this is only close to accurate for 64-bit divs. Checking any resource
(Agner Fog, uops.info) shows that narrows divs are much faster.
On my own machine (Xeon W-2191B) I wrote a test program which is able to retire
a 32-bit div every 6 cycles, exactly matching Agner Fog's claim.
I don't have a machine to test on but I am guessing all of this is true on
Skylake Client as well.
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