https://bugs.llvm.org/show_bug.cgi?id=41813
Bug ID: 41813
Summary: [X86] Improve HADD/HSUB shuffle combining
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: llvm-...@redking.me.uk
CC: craig.top...@gmail.com, llvm-bugs@lists.llvm.org,
llvm-...@redking.me.uk, spatel+l...@rotateright.com
As noted in https://reviews.llvm.org/D61308, we should try harder to combine
shuffles on either side of a HADD/HSUB instruction - possibly removing it in
the process. This may be true for PACK in some cases as well.
define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
; AVX-LABEL: PR22377:
; AVX: # %bb.0: # %entry
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,1]
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
; AVX-NEXT: retq
entry:
%s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32
3, i32 1, i32 3>
%s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32
2, i32 0, i32 2>
%r2 = fadd <4 x float> %s1, %s2
%s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32
4, i32 1, i32 5>
ret <4 x float> %s3
}
Under some circumstances we could even shuffle in +0.0f values into some lanes
so the HADD becomes inert.
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