https://bugs.llvm.org/show_bug.cgi?id=41535
Bug ID: 41535
Summary: [AArch64] Assertion `i != e && "VECTOR_SHUFFLE node
with all undef indices!"'
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AArch64
Assignee: unassignedb...@nondot.org
Reporter: efrie...@quicinc.com
CC: arnaud.degrandmai...@arm.com,
llvm-bugs@lists.llvm.org, peter.sm...@linaro.org,
spatel+l...@rotateright.com, ties.st...@arm.com
llc: [...]/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:9353: static bool
llvm::ShuffleVectorSDNode::isSplatMask(const int *, llvm::EVT): Assertion `i !=
e && "VECTOR_SHUFFLE node with all undef indices!"' failed.
Started showing up this week on
http://lab.llvm.org:8011/builders/aosp-O3-polly-before-vectorizer-unprofitable
. I'm pretty sure this is a regression from https://reviews.llvm.org/D60545
("[DAGCombiner] narrow shuffle of concatenated vectors"). I didn't properly
bisect, but it's the only relevant commit in the failure range.
Reduced testcase (crashes with "llc"):
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-android"
define void @f(i32 %src2, <16 x i8>* %tmp27) {
entry:
%tmp1 = insertelement <2 x i32> undef, i32 %src2, i32 0
%tmp6 = mul <2 x i32> %tmp1, <i32 2, i32 3>
%tmp7 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <4 x i32> <i32 0, i32
1, i32 undef, i32 undef>
%tmp9 = mul nsw <2 x i32> %tmp1, <i32 3, i32 3>
%tmp10 = shufflevector <2 x i32> %tmp9, <2 x i32> undef, <4 x i32> <i32 0,
i32 undef, i32 undef, i32 undef>
%tmp11 = insertelement <4 x i32> undef, i32 2, i32 2
%tmp12 = shufflevector <4 x i32> %tmp11, <4 x i32> undef, <4 x i32> <i32 0,
i32 1, i32 2, i32 4>
%tmp13 = shufflevector <4 x i32> undef, <4 x i32> %tmp7, <4 x i32> <i32 0,
i32 4, i32 5, i32 undef>
%tmp14 = shufflevector <4 x i32> %tmp13, <4 x i32> %tmp10, <4 x i32> <i32 0,
i32 1, i32 2, i32 4>
%tmp15 = add nsw <4 x i32> %tmp12, %tmp14
%tmp16 = extractelement <4 x i32> %tmp15, i32 2
%tmp17 = insertelement <16 x i32> undef, i32 %tmp16, i32 13
%tmp18 = extractelement <4 x i32> %tmp15, i32 3
%tmp19 = insertelement <16 x i32> %tmp17, i32 %tmp18, i32 14
%tmp26 = trunc <16 x i32> %tmp19 to <16 x i8>
store <16 x i8> %tmp26, <16 x i8>* %tmp27, align 1
ret void
}
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