https://bugs.llvm.org/show_bug.cgi?id=41231
Bug ID: 41231
Summary: Regression in "[ARM] Add missing memory operands to a
bunch of instructions", with error "Expected a variant
SchedClass"
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected]
Created attachment 21672
--> https://bugs.llvm.org/attachment.cgi?id=21672&action=edit
Reproduction source
Since SVN r356963, "[ARM] Add missing memory operands to a bunch of
instructions.", compilation of many different source files for
armv7-w64-mingw32 often fails with the error "Expected a variant SchedClass"
This can be reproduced with the attached reduced source file like this:
$ clang -target armv7-w64-mingw32 -c atrac-preproc.c -O3 -w
fatal error: error in backend: Expected a variant SchedClass
clang-9: error: clang frontend command failed with exit code 70 (use -v to see
invocation)
clang version 9.0.0 (trunk 356964) (llvm/trunk 356963)
Target: armv7-w64-windows-gnu
Thread model: posix
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