https://bugs.llvm.org/show_bug.cgi?id=40643
Bug ID: 40643
Summary: [AMDGPU][MC] Missing register size check for VOP3
operands
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: unassignedb...@nondot.org
Reporter: dpreobrazhen...@luxoft.com
CC: llvm-bugs@lists.llvm.org
VOP3 instructions do not check register size for operands with modifiers. The
following code should trigger errors, but it is assembled without any issues:
v_add_f32 v0, s[0:1], v0 // src0 should be a 32-bit register
v_add_f32 v0, v[0:1], v0 // src0 should be a 32-bit register
v_add_f64 v[0:1], s0, v[0:1] // src0 should be a 64-bit register
v_add_f64 v[0:1], v0, v[0:1] // src0 should be a 64-bit register
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