https://bugs.llvm.org/show_bug.cgi?id=39893
Bug ID: 39893
Summary: Assertion failed: `NumElements > 0 && "#Elements of a
VectorType must be greater than 0"'
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Common Code Generator Code
Assignee: unassignedb...@nondot.org
Reporter: russell_gal...@sn.scee.net
CC: llvm-bugs@lists.llvm.org
$ cat test.cpp
typedef int __attribute__((ext_vector_type(2))) d;
typedef char __attribute__((ext_vector_type(2))) e;
typedef char __attribute__((ext_vector_type(8))) f;
typedef union {
d a;
f b;
} g;
f h;
d j;
void k() {
g l;
l.a = - j;
volatile e m = __builtin_shufflevector(h, l.b, 10, 4);
}
$ clang -c -O1 test.cpp
clang-8: .../llvm/lib/IR/Type.cpp:607: static llvm::VectorType*
llvm::VectorType::get(llvm::Type*, unsigned int): Assertion `NumElements > 0 &&
"#Elements of a VectorType must be greater than 0"' failed.
Introduced at r345602.
Author: Sanjay Patel <spa...@rotateright.com>
Date: Tue Oct 30 14:14:34 2018 +0000
[DAGCombiner] narrow vector binops when extraction is cheap
Narrowing vector binops came up in the demanded bits discussion in D52912.
I don't think we're going to be able to do this transform in IR as a
canonicalization
because of the risk of creating unsupported widths for vector ops, but we
already have
a DAG TLI hook to allow what I was hoping for: isExtractSubvectorCheap().
This is
currently enabled for x86, ARM, and AArch64 (although only x86 has existing
regression
test diffs).
This is artificially limited to not look through bitcasts because there are
so many
test diffs already, but that's marked with a TODO and is a small follow-up.
Differential Revision: https://reviews.llvm.org/D53784
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