https://bugs.llvm.org/show_bug.cgi?id=39830
Bug ID: 39830
Summary: [llvm-mca] Investigate how to improve the load/store
queue usage simulation in LSUnit.
Product: tools
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: llvm-mca
Assignee: unassignedb...@nondot.org
Reporter: andrea.dibia...@gmail.com
CC: andrea.dibia...@gmail.com, llvm-bugs@lists.llvm.org,
matthew.da...@sony.com
On some processors, load/store operations are split into multiple uOps. For
example, X86 AMD Jaguar natively supports 128-bit data types, but not 256-bit
data types. So, a 256-bit load is effectively split into two 128-bit loads, and
each split load consumes one 'LoadQueue' entry. For simplicity, this class
optimistically assumes that a load instruction only consumes one entry in the
LoadQueue. Similarly, store instructions only consume a single entry in the
StoreQueue.
In future, we should reassess the quality of this design, and consider
alternative approaches that let instructions specify the number of load/store
queue entries which they consume at dispatch stage.
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