https://bugs.llvm.org/show_bug.cgi?id=39099
Bug ID: 39099
Summary: [LV] predicated strided loads vectorized as
interleave-group without masking
Product: libraries
Version: trunk
Hardware: All
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Loop Optimizer
Assignee: unassignedb...@nondot.org
Reporter: dorit.nuz...@intel.com
CC: llvm-bugs@lists.llvm.org
Created attachment 20933
--> https://bugs.llvm.org/attachment.cgi?id=20933&action=edit
testcase
There’s a bug in how we currently handle predicated strided loads -- we end up
vectorizing them without a mask... :
When strided loads are predicated, each of them will form an interleaved-group
(with gaps). However, subsequent stages of vectorization (planning and
transformation) assume that if a load is part of an Interleave-Group it is not
predicated, resulting in wrong code - unmasked wide loads are created.
Compiling the attached testcase with:
opt -loop-vectorize -enable-interleaved-mem-accesses -force-vector-width=8
-march=skx -S predicated-interleaved-bug.ll
you'll see we happily generate unmasked wide-loads and shuffles:
vector.body:
...
%wide.vec = load <16 x i8>, <16 x i8>* %5, align 1
%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32>
<i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%6 = or <8 x i32> %1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32
1>
...
%wide.vec1 = load <16 x i8>, <16 x i8>* %10, align 1
%strided.vec2 = shufflevector <16 x i8> %wide.vec1, <16 x i8> undef, <8 x
i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
...
The fix is simple - don’t allow analyzeInterleaving() open an interleave group
if the load/store is predicated. I'll upload the fix shortly.
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