https://bugs.llvm.org/show_bug.cgi?id=37989
Bug ID: 37989
Summary: [DAGCombine] Call
TargetLowering::SimplifyDemandedVectorElts from
supported ops
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected],
[email protected], [email protected],
[email protected]
As mentioned on [Bug #37890], we currently only use SimplifyDemandedVectorElts
in the DAGCombiner DAGCombiner::visitVECTOR_SHUFFLE.
We should add support/tests for calling from DAGCombiner::vist* for all the
supported vector ops:
ISD::CONCAT_VECTORS
ISD::INSERT_SUBVECTOR (and add ISD::EXTRACT_SUBVECTOR support)
ISD::INSERT_VECTOR_ELT (and call from DAGCombiner::visitEXTRACT_VECTOR_ELT)
ISD::VSELECT
Other possible useful operations to add include the various ISD::*EXTEND ops
and we should support passthrough handling of the same AND/OR/XOR/ADD/SUB/MUL
(+SHL/SRL/SRA?) operations as InstCombiner::SimplifyDemandedVectorElts.
Once those are in place we can start adding any necessary target opcodes
through SimplifyDemandedVectorEltsForTargetNode etc.
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