https://bugs.llvm.org/show_bug.cgi?id=37941
Bug ID: 37941
Summary: [AMDGPU][MC][GFX9] Invalid number of src operands for
ds_[read/write]_addtid_b32
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
LLVM AMDGPU assembler expects 1 src operand (an address) for these opcodes:
ds_read_addtid_b32 v7 v8 offset:65535
SP3 assembler assumes that these instructions have no src operands:
ds_read_addtid_b32 v7 offset:65535
AMD documentation states: "no part of the address comes from a VGPR".
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