https://bugs.llvm.org/show_bug.cgi?id=37131
Bug ID: 37131
Summary: [X86] Review current scheduler classes to minimise
need for InstRW overrides
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected],
[email protected]
Depends on: 32857, 35608, 36726, 36911, 36924, 36930, 36931
Blocks: 32325, 35548
Many models are making very poor use of the default scheduler classes, with
many using InstrRW, resulting in cases such as:
1 - A default class isn't used at all, and all its instructions use InstrRW -
we should be able to at least move some instructions to the default, or split
the class to match as many instructions as possible across all targets.
2 - An instruction uses InstrRW but in fact matches the default class values
(Bug #35548).
3 - Some targets just don't need to use some scheduler classes at all (Bug
#35608).
This patch is to track possible splits to the classes that would help us move
away from unnecessary InstRW usage and make the scheduler models more easily
maintainable.
Referenced Bugs:
https://bugs.llvm.org/show_bug.cgi?id=32325
[Bug 32325] [META][X86] Improve implementation and use of X86 scheduler models
https://bugs.llvm.org/show_bug.cgi?id=32857
[Bug 32857] Add scheduler classes for vector masked load/store operations
https://bugs.llvm.org/show_bug.cgi?id=35548
[Bug 35548] [X86] Warn if a scheduling instrs/instregex entry doesn't alter the
default schedule
https://bugs.llvm.org/show_bug.cgi?id=35608
[Bug 35608] [X86] Remove Schedule classes from models that don't use them
https://bugs.llvm.org/show_bug.cgi?id=36726
[Bug 36726] [X86][SSE] Split gpr/vector WriteMove, WriteLoad, WriteStore
scheduler classes
https://bugs.llvm.org/show_bug.cgi?id=36911
[Bug 36911] [X86] Add scheduler classes that account for GPR<->XMM transfers
https://bugs.llvm.org/show_bug.cgi?id=36924
[Bug 36924] [X86] Split vector schedule classes by vector width only as
necessary
https://bugs.llvm.org/show_bug.cgi?id=36930
[Bug 36930] [X86] Split WriteIDiv into 8/16/32/64 implementations
https://bugs.llvm.org/show_bug.cgi?id=36931
[Bug 36931] [X86] Split WriteIMul into 8/16/32/64 implementations
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