https://bugs.llvm.org/show_bug.cgi?id=36951
Bug ID: 36951
Summary: [X86] SandyBridge/Haswell/Broadwell/Skylake scheduler
models lose the ReadAdvance information for all
instructions that load from memory and read another
operand from a register
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: craig.top...@gmail.com
CC: llvm-bugs@lists.llvm.org
For example
[0,0] DeER . . addl %edi, %esi
[0,1] D=eeeeeeER addl (%rdi), %esi
The second instruction shouldn't have to wait on the first instruction to
writeback before it can execute.
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