https://bugs.llvm.org/show_bug.cgi?id=36851
Bug ID: 36851
Summary: [AMDGPU][MC] Unaligned SGPR pairs/quads/etc are
disassembled as if they were aligned
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: unassignedb...@nondot.org
Reporter: dpreobrazhen...@luxoft.com
CC: llvm-bugs@lists.llvm.org
This is a generic problem which affects both dst and src SGPR operands with
size greater than 32. These operands must be aligned to 2 or 4 so encoding an
odd register is incorrect and would trigger an exception if executed.
Our implementation defines only valid pairs of registers, e.g. s[0:1] but not
s[1:2] so correct disassembly is not possible. Currently disassembler issues a
warning and uses a nearest correctly aligned pair/quad of registers. (Due to
llvm disassembler quirk, the warning is not printed.)
Technically speaking, it is possible to define all incorrect register
pairs/quads etc but this looks like an overkill to me.
Personally I think current implementation is fine and needs no changes.
What is your opinion?
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