https://bugs.llvm.org/show_bug.cgi?id=36106
Bug ID: 36106
Summary: [AArch64][GlobalSel] Incorrect half to single
precision code gen
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: carey.willi...@arm.com
CC: llvm-bugs@lists.llvm.org
Created attachment 19756
--> https://bugs.llvm.org/attachment.cgi?id=19756&action=edit
Generated ASM
I believe there is a bug in the GlobalISel -0O code generation that affects
AArch64's half-precision (FP16) mechanics.
The generated code tries to convert a float value from single precision to
half-precision via FCVT. The problem is that in this case the immediate value
it is operating on is actually already stored/encoded in the half-precision
format.
Minimal reproducer:
int main() {
_Float16 b = 1024.0f16;
return (float)b;
}
Compiled with: clang -S -O0 -mllvm -aarch64-enable-global-isel-at-O=0
--target=aarch64-arm-none-eabi -march=armv8.2-a+fp16
Passing -mllvm -aarch64-enable-global-isel-at-O=-1 instead will generate
correctly functioning code.
---
I've attached the problematic generation with some comments.
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