https://bugs.llvm.org/show_bug.cgi?id=34733
Bug ID: 34733
Summary: Moffs operands are not encoded
Product: libraries
Version: 4.0
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: kadircetinkaya.06...@gmail.com
CC: llvm-bugs@lists.llvm.org
LLVM is not able to generate instructions with moffs operands, when I try to
assemble
mov al, [0x01]
with llvm-mc it generates encoding, [0x8a,0x04,0x25,0x01,0x00,0x00,0x00] which
is an instruction that actually uses full modr/m and sib. Which should decode
into mov al, byte ptr [0x01].
It should've generated "\xa0\x01\x00\x00\x00\x00\x00\x00\x00". As mentioned in
page 45 of Intel SDM, Instruction Set Reference, July 2017.
"
2.2.1.4 Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended
to specify a 64-bit immediate absolute address. This address is called a
moffset. No prefix is needed to specify this 64-bit memory offset. For these
MOV instructions, the size of the memory offset follows the address-size
default (64 bits in 64-bit mode). See Table 2-6.
"
Somehow,
http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+al%2C+%5B0x01%5D&arch=x86-64#assembly
this assembler manages to do it even tough they are using Keystone and
Capstone. May be it was correct in previous versions, and got broken in a later
release?
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