https://bugs.llvm.org/show_bug.cgi?id=34106
Bug ID: 34106
Summary: ARMTargetLowering::isLegalAddressingMode can accept
incorrect addressing modes for Thumb1 target
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
Assignee: unassignedb...@nondot.org
Reporter: eas...@yandex.ru
CC: llvm-bugs@lists.llvm.org
This bug report is a result of investigation of performance regressions on
Cortex-M0+ and Cortex-M23 triggered by the changes:
https://reviews.llvm.org/D34583
See a discussion thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170731/475927.html
for more information about the investigation.
The current code of ARMTargetLowering::isLegalAddressingMode:
bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
unsigned AS, Instruction *I)
const {
EVT VT = getValueType(DL, Ty, true);
if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
return false;
// Can never fold addr of global into load/store.
if (AM.BaseGV)
return false;
switch (AM.Scale) {
case 0: // no scale reg, must be "r+i" or "r", or "i".
break;
case 1:
if (Subtarget->isThumb1Only())
return false;
LLVM_FALLTHROUGH;
default:
// ARM doesn't support any R+R*scale+imm addr modes.
if (AM.BaseOffs)
return false;
if (!VT.isSimple())
return false;
if (Subtarget->isThumb2())
return isLegalT2ScaledAddressingMode(AM, VT);
For the Thumb1 target the code returns false when AM.Scale equals 1. It returns
true when AM.Scale equals 4, for example. AM.Scale == 1 which actually means no
scaling so the Thumb1 target can accept it. Other Scale values can be accepted
by the Thumb1 target because its addressing modes do not support scaling.
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