https://llvm.org/bugs/show_bug.cgi?id=31282
Bug ID: 31282
Summary: Terrible ARM shuffle lowering for blend with constant
zero
Product: libraries
Version: trunk
Hardware: All
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
Assignee: unassignedb...@nondot.org
Reporter: efrie...@codeaurora.org
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
Testcase:
define <8 x i8> @f(<8 x i8> %t) {
%r = shufflevector <8 x i8> <i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8
undef, i8 undef, i8 undef>, <8 x i8> %t, <8 x i32> <i32 0, i32 1, i32 10, i32
11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %r
}
With llc -mtriple=armv7--linux-gnueabihf:
vldr d18, .LCPI0_0
vorr d17, d0, d0
vmov.i32 d16, #0x0
vtbl.8 d0, {d16, d17}, d18
bx lr
By contrast, an equivalent "and" instruction generates the following:
vmov.i64 d16, #0xffffffffffff0000
vand d0, d0, d16
bx lr
(SROA likes to generate this sort of shuffle.)
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
