| Issue |
209102
|
| Summary |
[RISCV] computeKnownBits - add support for RISCVISD::VECREDUCE_ADD_VL
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
sabonaoabdi
|
`RISCVTargetLowering::computeKnownBitsForTargetNode` doesn't handle
`RISCVISD::VECREDUCE_ADD_VL`, so known bits are lost once an
`ISD::VECREDUCE_ADD` is lowered to the RISC-V vector-length (VL) form.
Context: #207631 added generic `computeKnownBits` support for
`ISD::VECREDUCE_ADD`. For fixed-length RVV reductions (e.g. the
sum-of-absolute-differences pattern), the reduction lowers to
`RISCVISD::VECREDUCE_ADD_VL`, which has no known-bits handling — so the
generic bound doesn't survive on that path. A mask that could otherwise
fold away (RISC-V's `vmv.x.s` already sign-extends the element to XLEN)
is instead materialized as an `slli`/`srli` pair. See the diffs in
`llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll`.
Adding a `computeKnownBitsForTargetNode` case for
`RISCVISD::VECREDUCE_ADD_VL` (and likely the sibling `*_VL` reduction
nodes) would recover the bound.
Complication: unlike the generic node,
`VECREDUCE_ADD_VL` operates on scalable vectors and takes the vector
length as a runtime operand, so there's no compile-time element
count to feed `KnownBits::reduceAdd(NumElts)`. Bounding the reduction
without a static element count is the non-trivial part.
Extends #206289.
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