https://llvm.org/bugs/show_bug.cgi?id=13633
Hal Finkel <hfin...@anl.gov> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
CC| |hfin...@anl.gov
Resolution|--- |FIXED
--- Comment #1 from Hal Finkel <hfin...@anl.gov> ---
This seems to be fixed now. For the test case provided, we now generate:
mflr 0
std 31, -8(1)
std 0, 16(1)
stdu 1, -160(1)
lis 3, 16404
mr 31, 1
addis 5, 2, .LCPI0_0@toc@ha
addis 6, 2, .LCPI0_1@toc@ha
addis 7, 2, .LCPI0_2@toc@ha
li 4, 3
li 9, 4097
ori 3, 3, 52428
lfd 2, 144(31)
lfd 1, .LCPI0_0@toc@l(5)
lfd 4, .LCPI0_1@toc@l(6)
sldi 3, 3, 32
lfd 5, .LCPI0_2@toc@l(7)
li 8, 127
sldi 4, 4, 32
oris 3, 3, 52428
std 8, 128(1)
sldi 9, 9, 50
std 4, 112(1)
ori 3, 3, 52429
li 5, 99
fmr 3, 2
li 8, 0
std 3, 120(1)
li 3, 23
bl func
nop
addi 1, 1, 160
ld 0, 16(1)
ld 31, -8(1)
mtlr 0
blr
There are no stores to r1+96 or r1+98.
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