https://llvm.org/bugs/show_bug.cgi?id=28925
Bug ID: 28925
Summary: [x86, SSE] failed to simplify vector select with zero
constant to 'andn'
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: spatel+l...@rotateright.com
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
Follow-up from bug 28895 / https://reviews.llvm.org/D23337 :
define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %r
}
Double-check the truth tables and x86 operand order, but I think this could be
'pandn' rather than 'blendv':
$ ./llc -o - -mattr=avx sel.ll
vpslld $31, %xmm0, %xmm0
vxorps %xmm2, %xmm2, %xmm2
vblendvps %xmm0, %xmm2, %xmm1, %xmm0
retq
-----------------------------------------------------------------------------
vpslld $31, %xmm0, %xmm0
vpsrad $31, %xmm0, %xmm0
vpandn %xmm1, %xmm0, %xmm0 ; ~%cond & %x
-----------------------------------------------------------------------------
In the normal case (?), we'd expect the compare instruction that produces the
condition operand to be in the function:
define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {
%cond = fcmp oeq <4 x float> %a, %b
%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %r
}
Currently, we handle this pattern by inverting the condition rather than using
'andn':
vcmpneqps %xmm0, %xmm1, %xmm0 ; fcmp oeq -> fcmp une
vandps %xmm2, %xmm0, %xmm0
retq
This is done in "combineVSelectWithAllOnesOrZeros()".
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
