https://llvm.org/bugs/show_bug.cgi?id=28895
Bug ID: 28895
Summary: [x86, SSE] failed to simplify vector select with zero
constant to 'and'
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: spatel+l...@rotateright.com
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
While looking at the select fold in https://reviews.llvm.org/D22975, I noticed
this problem:
define <4 x float> @fselvec(<4 x float> %x, <4 x float> %y) {
%cmp = fcmp oeq <4 x float> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x float> %y, <4 x float> zeroinitializer
ret <4 x float> %sel
}
This should be an 'and' bitwise logic op, but:
$ ./llc fsel.ll -o - -mattr=avx
vxorps %xmm2, %xmm2, %xmm2
vcmpeqps %xmm2, %xmm0, %xmm0
vblendvps %xmm0, %xmm1, %xmm2, %xmm0
retq
The optimization exists for AArch64:
$ ./llc fsel.ll -o - -mtriple=aarch64
fcmeq v0.4s, v0.4s, #0.0
and v0.16b, v1.16b, v0.16b
ret
The optimization also exists for x86 FP scalar and x86 integer vector, so some
refactoring may be needed:
define float @fsel(float %x, float %y) {
%cmp = fcmp oeq float %x, 0.0
%sel = select i1 %cmp, float %y, float 0.0
ret float %sel
}
define <4 x i32> @iselvec(<4 x i32> %x, <4 x i32> %y) {
%cmp = icmp eq <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> %y, <4 x i32> zeroinitializer
ret <4 x i32> %sel
}
_fsel: ## @fsel
vxorps %xmm2, %xmm2, %xmm2
vcmpeqss %xmm2, %xmm0, %xmm0
vandps %xmm1, %xmm0, %xmm0
retq
_iselvec: ## @iselvec
vpxor %xmm2, %xmm2, %xmm2
vpcmpeqd %xmm2, %xmm0, %xmm0
vpand %xmm1, %xmm0, %xmm0
retq
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
