https://llvm.org/bugs/show_bug.cgi?id=28601
Bug ID: 28601
Summary: [mc] New syntax for ds_swizzle_b32 offset
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: unassignedb...@nondot.org
Reporter: i.am.permi...@gmail.com
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
Swizzle pattern for ds_swizzle_b32 instruction is encoded in the offset field
of the instruction. It would be nice to have more friendly syntax then just hex
code. So new function swizzle() that construct a value is proposed.
syntax for quad permute mode:
swizzle(SWZL_QUAD_PERM, laneid0, laneid1, laneid2, laneid3)
where "laneid*" is integer from 0 to 3
syntax for bitmask mode:
swizzle(SWZL_BITMASK, mask)
where "mask" is 5 character sequence with allowed characters:
"0" - set to 0
"1" - set to 1
"p" - preserve
"i" - inverse
additional syntax for common cases of bitmask mode:
swizzle(SWZL_BCAST, gsize, laneid)
where gsize is (1|2|4|8|16|32) and laneid is integer from 0 to (gsize-1)
swizzle(SWZL_SWAP, gsize)
where gsize is (1|2|4|8|16)
swizzle(SWZL_MIRROR, gsize)
where gsize is (2|4|8|16|32)
examples:
swizzle(SWZL_QUAD_PERM, 2, 1, 3, 3) equals 0x80F6
swizzle(SWZL_BITMASK, pppii) equals 0x0C1F
swizzle(SWZL_MIRROR, 4) equals 0x0C1F
swizzle(SWZL_BITMASK, pippp) equals 0x401F
swizzle(SWZL_SWAP, 16) equals 0x401F
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