https://llvm.org/bugs/show_bug.cgi?id=28138
Bug ID: 28138
Summary: trunk/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp: 2
* wierd conditions ?
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedb...@nondot.org
Reporter: dcb...@hotmail.com
CC: llvm-bugs@lists.llvm.org
Classification: Unclassified
1.
trunk/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:1533] ->
[trunk/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:1533]: (style) Same
expression on both sides of '||'.
Source code is
if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
Maybe better code
if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
2.
trunk/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:3678] ->
[trunk/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:3678]: (style) Same
expression on both sides of '&&'.
Source code is
if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
maybe better code
if (isIntRegForSubInst(Src1Reg) &&
MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) &&
MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
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