https://llvm.org/bugs/show_bug.cgi?id=26358
Bug ID: 26358
Summary: [AArch64] Add paired loads/stores to
getMemOpBaseRegImmOfsWidth()
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: normal
Priority: P
Component: Backend: AArch64
Assignee: mcros...@codeaurora.org
Reporter: mcros...@codeaurora.org
CC: bma...@codeaurora.org, gbe...@codeaurora.org,
haich...@codeaurora.org, junb...@codeaurora.org,
llvm-bugs@lists.llvm.org, mssim...@codeaurora.org
Classification: Unclassified
The target specific hook areMemAccessesTriviallyDisjoint() is used by the MI
scheduler to determine if two memory access are disjoint (i.e., don't alias).
The helper function getMemOpBaseRegImmOfsWidth() should include all of the
paired instructions (e.g., STPSi, LDPSi, etc.), so the scheduler has more
flexibility when scheduling.
First http://reviews.llvm.org/D8705 needs to land, so the scheduler better
handles instructions with multiple MMOs. Then mergePairedInsns() in the
AArch64 load store optimizer needs to be fixed so that the pair instructions
include their MMOs. Once complete then paired instructions can be added to the
getMemOpBaseRegImmOfsWidth() function.
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